1. Field of the Invention
This application relates to analog-to-digital converters and more particularly to calibration of time-interleaved analog-to-digital converters.
2. Description of the Related Art
High speed analog-to-digital converters (ADCs) are key building blocks to applications such as software defined radio and TV tuners. A software defined TV tuner requires a high speed ADC that fully captures the cable TV signal which spans the frequency band 50 MHz-1 GHz. Such a high speed ADC should provide around 60 dB of signal to noise and distortion ratio (SNDR) while operating at a sampling frequency (fs) of 3˜4 gigasamples (GS)/s.
Referring to FIG. 1, a high speed analog to digital converter 100 can be efficiently achieved by interleaving a number (M) of sub-ADCs 101. In various embodiments of analog to digital converters, the ADC tracks the input signal (ADC In) for a period of time and then holds the tracked signal for conversion to digital and that operation is referred to as track and hold. The sample clocks shown as (φ1, φ2, . . . , φM) in FIG. 1 control the track and hold operation. The sampled analog value may be held, e.g., in a capacitive circuit, and supplied to conversion circuitry to convert the analog signal to digital over a sample period. The sampling instant (φ1, φ2, . . . , φM) of each sub-ADC 101 is ideally offset by one ADC sampling clock period (Ts) from the preceding sub-ADC. That effectively supplies the input to one of the M sub-ADCs at a time. Interleaving allows more conversion time of (MTs) for each sub-ADC. The sub-ADC digital outputs (D1, D2, . . . , DM) are finally combined (i.e. interleaved) to generate the full-rate ADC output 102 using selector 103. The interleaved architecture allows each sub-ADC to run at a lower speed of fclk=fs/M which simplifies the sub-ADC design, where fs is the full-rate ADC sampling frequency. Assuming the sub-ADCs perfectly match, the time-interleaved ADC operates seamlessly like a single high-speed ADC.
In practice, sub-ADCs have mismatch in their offset, gain, bandwidth, and sampling instant. FIG. 2 shows a model for a time-interleaved ADC with gain mismatches (Gi) 201, offset mismatches (Oi) 203, and timing mismatches (φi(t-τi) 205. Such mismatches cause conversion errors and introduce spurs in the ADC output. Offset mismatch adds a fixed pattern to the ADC output that repeats every M samples. That pattern is input-signal independent and introduces spurs at frequencies Nfs/M, N=1, . . . , M−1. Gain mismatch modulates the input signal amplitude and introduces spurs at Nfs/M±fin where fin is the frequency of the input signal. The magnitude of these spurs is proportional to the input signal amplitude. Similarly, timing mismatch modulates the phase of the input signal and introduces spurs at Nfs/M±fin. The amplitude of these spurs is a function of the input signal derivative, which for a sinusoidal input is proportional to both its amplitude and frequency. While gain errors are frequency independent, timing errors are more significant for high frequency inputs, and hence are typically the dominant error source for high speed designs.
Bandwidth mismatch introduces both gain mismatch and delay mismatch that are frequency dependent. For sufficiently wide input track-and-hold (T/H) bandwidth and moderate mismatches, the frequency dependence of the delay mismatch can be ignored to a first order, and therefore it can be treated as a fixed timing skew. That is similar to clock skew, but here the signal itself is being delayed rather than the clock. As for gain mismatch, its significance depends on the application. For single tone inputs, the gain error would be significant for high frequency inputs. For wide band inputs, e.g. cable TV signal, the input contains lower high frequency content and therefore less gain error would be generated due to this gain mismatch. Additionally, if a large interleaving factor (M), e.g. 64, is used, this would ensure that the gain error power is distributed across the whole TV band and has a lower power spectral density. Therefore, the gain error contribution to each TV channel band becomes small. That is opposed to using a small interleaving factor and having the gain error power concentrated within a small band of channels.
In general, mismatches can be calibrated either in foreground or background. In foreground calibration, calibration occurs while analog signals are not otherwise being processed. Background calibration occurs during system operation while analog signals are being converted to digital for system use. Background calibration is often necessary for achieving high resolution, given its ability to track voltage and temperature variations. Background calibration of timing errors is the most challenging and remains a topic of active research.
In general, calibration of an interleaved ADC involves two steps, namely, detection and correction of mismatch errors. As for timing calibration, correction of timing skew mismatch can be achieved either in the analog domain using programmable delay elements, or in the digital domain using adaptive digital filters. The analog approach is less complex and has been adopted in most practical implementations. As for timing skew mismatch detection, a number of techniques exist. These techniques can be classified into three categories: i) Calibration signal based, ii) Reference ADC based, iii) Input signal statistics based. A sawtooth calibration signal with period (M+1)Ts/N may be added to the input signal. Assuming zero offset for each sub-ADC, the average of each sub-ADC output can be used as a measure of its timing skew. As the input signal represents large uncorrelated noise source for the measurement of timing skew error, the sawtooth amplitude has to be large for reasonable convergence time. That decreases signal dynamic range. Therefore, a trade-off exists between signal dynamic range and convergence speed. In one prior art approach, the calibration signal occupied 25% of the ADC full scale.
In the second category, a reference ADC, without a calibration signal, is used to enable fast convergence for the calibration algorithm. The timing error of sub-ADC k, referred to as ADCk, is taken as the difference between the reference ADC and ADCk outputs. As the input signal is common to both outputs, it gets cancelled and therefore less averaging and faster convergence is possible. Unlike the previous category where an input calibration signal with a known derivative was used, the input signal derivative has to be estimated in this second category. That may be done using analog derivative estimators, or digital derivative estimators, with the former approach being more accurate. While the use of a reference ADC speeds up convergence, the dependence on the input signal statistics for measurement of timing error can slow down convergence.
In the third approach, timing error is detected from the cross correlation of sub-ADC outputs. For example, a reference ADC may be used and cross correlation is performed between each sub-ADC and the reference. In another approach, cross-correlation is performed between sub-ADC outputs eliminating the need for a reference ADC. Advantage of this technique is that it does not require a calibration signal and it also simplifies the implementation of the reference ADC. However, the drawback is that it places restrictions on the input signal and also its convergence time is a function of input signal activity.
Thus, improvements in background calibration are desirable.